Integrating camera capture and display subsystems on embedded SoCs presents significant software design challenges due to competing buffer ownership models across independent hardware subsystems. This talk presents a practical implementation of a zero-copy video pipeline on a TI Jacinto SoCs running FreeRTOS, coordinating three drivers: a CSI2-DPHY receiver, a UDMA engine, and a Display Subsystem driver.
The implementation uses FVID2, TI's unified video interface, to apply a consistent queue/dequeue buffer model to both capture and display operations. We examine the initialization sequence where the application transfers UDMA ownership to the CSIRX driver, enabling the DSS driver direct visibility into captured buffers.
Critical gaps in single-task designs are identified, specifically the absence of mechanisms preventing capture from overwriting buffers during display scanout. We present a corrected two-task producer-consumer design using counting semaphores to enforce mutual exclusion, with explicit analysis of task priorities and frame timing implications.
This work bridges the gap between pipelines that function nominally and those structured to remain correct under timing pressure, illustrating the complexity beneath seemingly solved problems in embedded systems integration.
