RTL to Zephyr RTOS: Lightweight-Crypto Acceleration on Open RISC-V

Lightweight cryptography is the solution for resource-constrained embedded devices. Ascon was the finalists in NIST Lightweight Cryptography Standardization Process, chosen from a set of finalists that includes Romulus, built on the SKINNY block cipher. But standardizing an algorithm is not the same as making it cheap to run on a microcontroller.

In this talk, the author shows a fully open path from hardware to Zephyr RTOS: a lightweight crypto co-processor written in VHDL, integrated into the open NeoRV32 RISC-V soft-core, and exposed to applications through Zephyr RTOS. The author walks through one working example end to end, a SKINNY-AEAD accelerator on an FPGA board, validated on real hardware against the reference test vectors, and driven from Zephyr over a memory-mapped register.

The author then generalize it into a repeatable recipe register interface, devicetree binding, driver, crypto API integration, that applies to Ascon and the other NIST Lightweight cryptography finalists.

Zephyr community, it contributes a concrete NeoRV32 plus crypto-accelerator reference, a worked devicetree binding and driver pattern for memory-mapped crypto cores, and a candid discussion of how lightweight crypto and open silicon fit the legacy crypto API and the PSA Crypto direction.

For Zephyr RTOS and open-source ecosystem, it lowers the barrier to experimenting with NIST lightweight cryptography on open RISC-V, and it contributes a concrete Open RISC-V crypto-accelerator reference