Can We Design a Chip Without Cadence?

Can we take a digital design from Verilog code to a physical chip layout using open-source tools?

I wanted to find out, so I built a 4-bit ALU and took it through an open-source ASIC design flow using tools like Icarus Verilog, Yosys, OpenLane, KLayout, and the SkyWater SKY130 PDK.

My OpenLane run reported passing DRC, LVS, and antenna checks…

The process wasn't as smooth as I expected. I ran into many tool compatibility issues, struggled with setting up WSL and Docker, and spent time understanding the synthesis results and physical layout.

In this talk, I'll share how I approached the project, the challenges I faced, what helped me work through them, and what I learned along the way.

With tools like Cadence being familiar in the EDA space, I wanted to explore how far open-source tools could take a small digital design.

By the end of the talk, you'll have a clearer understanding of how a simple Verilog design can go from code to a physical layout using open-source tools.

>Learn how a Verilog design becomes a chip layout.
>Understand the RTL-to-GDSII workflow using open-source EDA tools.

>Learn how Icarus Verilog, Yosys, OpenLane, KLayout, and SKY130 work together.