Open-Source VLSI Tools: An Overview with a Front-End Design Walkthrough

This session introduces the ecosystem of open-source VLSI tools to the audience and explain how they can be used to understand and implement the front-end digital design flow in a practical and approachable way.

VLSI design is often seen as inaccessible due to the heavy reliance on costly proprietary EDA tools. This creates a significant barrier for students, educators and early-stage engineers who want to explore chip design beyond theory. Through this talk, we aim to show that it is entirely possible to learn and experiment with digital design using free and open-source tools, without compromising on core concepts.

The session will begin with a brief overview of the open-source tools available in the VLSI ecosystem and where they fit in the overall RTL-to-GDSII flow. We will then focus specifically on the front-end digital design stages, starting from RTL coding and functional verification and moving on to logic synthesis.

Using small and easy-to-follow examples such as multiplexers and flip-flops, we will demonstrate how:

• Icarus Verilog (iverilog) is used to write and simulate Verilog RTL designs

• GTKWave helps in visualizing waveforms and debugging functional behaviour

• Yosys is used to synthesize RTL into a gate-level netlist using standard cell libraries

The session will also cover common RTL coding mistakes, how synthesis tools understand hardware intent and why verifying designs at the RTL stage is important before moving ahead in the flow. Instead of focusing only on tool commands, the talk aims to build a clear understanding of how digital hardware is created from code.

• Overview of open-source tools available for VLSI design

• Clear understanding of the front-end digital design flow

• Demo-based walkthrough of RTL simulation and debugging with open-source tools

• How synthesis transforms Verilog code into hardware structures

• Confidence to start learning VLSI design without proprietary tools