OpenCDC — Open-source Clock Domain Crossing Analyser
A static RTL analysis tool that detects CDC violations in Verilog designs — the open-source alternative to $100K/year commercial EDA tools.
Clock Domain Crossing (CDC) bugs are the leading cause of ASIC re-spins,
costing $1M+ per iteration at real fabs. Commercial CDC checkers
(JasperGold, SpyGlass) cost $100,000+/year. No credible open-source
alternative exists.
OpenCDC is a Python-based static analysis tool that:
- Parses synthesised Verilog/RTL netlists using Yosys + PyVerilog
- Extracts and labels clock domains using graph traversal (NetworkX)
- Detects CDC violations: missing synchronisers, async reset crossings
- Generates an interactive HTML report with a coloured domain graph
Target demo: run on PicoRV32 (open-source RISC-V core) and surface
real crossing violations.
License: MIT
Stack: Python, Yosys, PyVerilog, NetworkX, Graphviz